Due to the increasing limitation of wafer-scale integration, in terms of cycle time and technology integration, significant advancements are being made in the area of multi-die packaging (e.g.: stacked-die package). Additionally, there is pressure from the semiconductor industry to reduce overall package size requirements that encompass both footprint area and package height. The package-height constraint results in thinner and thinner dies being stacked in a single package. However, there are limitations in the ability to stack dies of numerous sizes, shapes, and thickness in the desired configurations.
Currently, paste and elastomeric film adhesives are used to attach semiconductor die to the laminated substrate. The benefit of paste adhesives is that during the assembly process, the paste has viscous properties that accommodate irregular topographical features on the substrate and minimize the formation of die attach voids.
However, there are disadvantages to using paste adhesive. In particular, thin dies often have significant warpage. During the die attach process, the pick & place tool will hold the die substantially flat while the die is in contact with the paste. However, due to the viscous nature of paste adhesives, when the pressure from the pick & place tool is removed, the die will have a strong tendency to return to a warped shape. The result is undesirable non-uniform bond line thickness, which makes subsequent processing steps, such as wirebonding or die stacking, more difficult. Die attach paste also has a tendency to shrink during the curing process and the shrinkage may produce a reverse fillet that extends under the edge of the die rather than upward along the side walls of the die.
Film adhesives have the advantage of providing a uniform bond line thickness and do not shrink appreciably during the curing process. However, due to the rather rigid nature of film adhesives, topographical features on the substrate surface tend to cause interfacial voids between the bottom of the film adhesive and the surface of the substrate. The formation of such voids is undesirable, both from an assembly yield and reliability perspective. The presence of interfacial voids results in less than optimal adhesion and can trap moisture that expands and causes de-lamination during post-assembly temperature excursions. The voids are caused by the shapes of the surface variations themselves and by air that is trapped due to feature patterns that provide no exit for air during die mounting.
One method used to minimize topographical variations of the substrate is a fill of all areas around electrical traces with solid metal. However, solid regions of metal tend to be thicker that the metal traces due to etching/plating density, resulting in less than ideal planarity. Further, it is very important that the top solder mask layer and the underlying prepreg layer on either side of the top metal layer have sufficient contact to provide adhesion.
An alternative method of providing a substantially flat surface for attaching via film adhesive is planarizing the substrate, using a filler material and a mechanical grinding technique, prior to applying the top layer of solder mask. The disadvantage of mechanical planarization is a lack of technology available for high-volume manufacturing. Due to the need to incorporate filler material and due to the cost of the additional processing, it will likely be some time before the technique becomes a viable option and the industry fully adopts the technique.
Therefore, it would be desirable to provide a low cost and low processing overhead method and substrate for film-mounting semiconductor dies that overcomes problems associated with film-mounting a die over conductive pattern features on the surface of the substrate.